In a semiconductor integrated circuit, to control individual elements in a completely independent state by avoiding electrical interference between the elements during the operation, an element isolation structure having an element isolation region needs to be formed. As one of methods of forming such an element isolation region, trench isolation is widely known, and various improved methods have been devised.
The trench isolation method is a method of forming a trench on a substrate and filling the trench with an insulator. Because a bird's beak hardly occurs, this method can be an effective element isolation method in miniaturizing a semiconductor integrated circuit. On the other hand, it is pointed out that along the miniaturization of elements, potentials of adjacent elements affect other nodes via an embedded oxide film. To cope with this problem, a method of embedding a conductive film into the trench has been proposed.
A conventional semiconductor device and a conventional manufacturing method having a conductive film embedded in the trenches are explained with reference to FIG. 39 to FIG. 44. As shown in FIG. 39 and FIG. 40, in the conventional semiconductor device, a polysilicon film 104 is filled in a trench 102 formed in a semiconductor substrate 101, via a silicon oxide film 103. A cap oxide film 111 is formed on the polysilicon film 104 inside the trench 102. A gate electrode 107 is formed in an active region of an element via a gate insulating film 106, and a source/drain diffusion layer 108 is formed via a channel region beneath the gate electrode 107. A sidewall 115 is formed on a side surface of the gate electrode 107.
The conventional method of manufacturing a semiconductor device is explained next. A silicon oxide film 109 and a silicon nitride film 110 are formed in this order on the semiconductor substrate 101. The silicon nitride film 110 and the silicon oxide film 109 are patterned, using a photoengraved pattern as a mask formed by a photoengraving technique and a dry etching technique, to form the trench 102 on the semiconductor substrate 101 as shown in FIG. 40.
After the trench 102 is formed, the surface of the inner wall of the trench 102 is thermal oxidized to remove the inner wall of the trench 102, that is, damaged parts of the inner surface and a bottom surface. The silicon oxide film 103 is formed on the inner wall of the trench 102 as shown in FIG. 41. Further, the polysilicon film 104 doped with phosphor is deposited on the entire surface of the semiconductor substrate 101 according to a CVD (chemical vapor deposition) method. A part of the polysilicon film 104 on the silicon nitride film 110 and in the trench 102 is removed by the anisotropic etching as shown in FIG. 42.
The polysilicon film 104 in the trench 102 is oxidized by thermal oxidation to form the cap oxide film 111 as shown in FIG. 43. The silicon nitride film 110 is removed, and the silicon oxide film 109 is removed to complete a trench-type element isolation structure as shown in FIG. 44. Thereafter, a well region, a channel cut region, and a channel impurity layer to control a threshold voltage are formed by the ion implantation method, following the known MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formation process. The gate insulating film 106 is formed on the semiconductor substrate 101, and the gate electrode 107 is formed on the gate insulating film 106. The source/drain diffusion layer 108 is formed by the ion implantation method, and the sidewall 115 is formed to complete the semiconductor device as shown in FIG. 39.
Patent Document 1: Japanese Patent Application Laid-open No. H6-232248
Patent Document 2: Japanese Patent Application Laid-open No. 2001-148418